Freescale Semiconductor /MK10F12 /I2S0 /TCR2

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Interpret as TCR2

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DIV0 (0)BCD 0 (0)BCP 0 (00)MSEL 0 (0)BCI 0 (0)BCS 0 (00)SYNC

MSEL=00, BCS=0, SYNC=00, BCI=0, BCD=0, BCP=0

Description

SAI Transmit Configuration 2 Register

Fields

DIV

Bit clock divide

BCD

Bit clock direction

0 (0): Bit clock is generated externally (slave mode).

1 (1): Bit clock is generated internally (master mode).

BCP

Bit clock polarity

0 (0): Bit Clock is active high (drive outputs on rising edge and sample inputs on falling edge).

1 (1): Bit Clock is active low (drive outputs on falling edge and sample inputs on rising edge).

MSEL

MCLK Select

0 (00): Bus Clock selected.

1 (01): Master Clock 1 selected.

2 (10): Master Clock 2 selected.

3 (11): Master Clock 3 selected.

BCI

Bit Clock Input

0 (0): No effect.

1 (1): Internal logic is clocked by external bit clock.

BCS

Bit Clock Swap

0 (0): Use the normal bit clock source.

1 (1): Swap the bit clock source.

SYNC

Synchronous Mode

0 (00): Asynchronous mode.

1 (01): Synchronous with receiver.

2 (10): Synchronous with another SAI transmitter.

3 (11): Synchronous with another SAI receiver.

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